From def87a2cbf0f4aacd6cd68d2c56ea58cc03a6b62 Mon Sep 17 00:00:00 2001 From: Keir Fraser Date: Fri, 23 Oct 2009 10:15:17 +0100 Subject: [PATCH] x86: Enable TSC_RELIABLE for AMD servers Except for a published BIOS errata on family 11h processors, all AMD servers that have the Invariant TSC bit set have a reliable TSC so Xen should not write to the TSC. Signed-off-by: Dan Magenheimer Acked-by: Mark Langsdorf --- xen/arch/x86/cpu/amd.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/xen/arch/x86/cpu/amd.c b/xen/arch/x86/cpu/amd.c index d7d3fe7cd7..94f35770e5 100644 --- a/xen/arch/x86/cpu/amd.c +++ b/xen/arch/x86/cpu/amd.c @@ -465,6 +465,8 @@ static void __devinit init_amd(struct cpuinfo_x86 *c) if (c->x86_power & (1<<8)) { set_bit(X86_FEATURE_CONSTANT_TSC, c->x86_capability); set_bit(X86_FEATURE_NONSTOP_TSC, c->x86_capability); + if (c->x86 != 0x11) + set_bit(X86_FEATURE_TSC_RELIABLE, c->x86_capability); } } -- 2.30.2